Conquering Memory Bandwidth Challenges in High-Performance SoCs

High end System‐on‐Chip (SoC) architectures consist of tens of processing engines. In SoCs targeted at high performance computing such as HDTV chips, the communication bandwidth is dominated by accesses to the off‐chip DRAM. Limited available bandwidth at the DRAM memory continues to be one of the most important constraints driving the design of these SoCs. Newer DRAM memories such as DDR‐3 impose a minimum access granularity that can lead to memory wastage when configured to attain the bandwidth requirements of the application. In this paper, we introduce and highlight multi‐channel DRAM memories in high‐performance SoCs as a solution for the memory bandwidth problem, and present our communications architecture optimized for the same. We will address deadlock scenarios associated with multi‐channel memories and provide mechanisms to avoid them. We compare our architecture with an industrial interconnect by experimenting with representative high definition digital TV applications. Our results indicate an average of 15% throughput improvement over the commercial interconnect solution.